Modern integrated circuits (ICs) are fabricated on semiconductor wafers that are mass produced in fabrication sites. The fabrications sites (or “fabs”) employ various types of automatic equipment that must function to very exacting and carefully controlled operating parameters. FIG. 1 depicts some of the process steps or modules found in a generic fab system 10. System 10 may be thought of as a track system 20 that comprises a variety of production modules, and a scanner (or stepper) system 30. Track system 20 typically operates synchronously under control of a computer system 40 that, among other tasks, outputs a track system clock signal (TRACK CLOCK). By synchronously it is meant that wafers are moved in the track system 20 responsive to the track clock signal.
The wafers under production are made available for input to the scanner system 30 responsive to the track clock signal. However scanner system 30 receives the wafers and outputs scanner system-completed wafers responsive to its internal scanner system clock (SCANNER CLOCK). Understandably much attention is given in the prior art to trying to synchronize the track clock and the scanner clock to reduce dead-time in moving and processing wafers through the overall fabrication system. But to achieve good synchronization between the track clock and the scanner clock, the timing in the scanner system must exhibit a substantially consistent periodicity. But in practice, exposure procedures within the scanner system can exhibit,a timing deviation from nominal periodicity, which deviation or variability hampers clock synchronization.
Exemplary modules within track system 20 are shown in FIG. 1. At the upper left region of FIG. 1, a sequence of wafers are input to system 20. A chill plate module 50 typically is used to stabilize the wafer temperature by about 1° C. to room temperature before the wafers enter a spin coater 60 where a film of polymer photoresist is placed on the upper surface of the wafer. In some processes, at step 60 an anti-reflection coating may first be deposited upon the upper wafer surface and the wafer then baked (e.g., module or step 70) and then returned to the spin coater 60 for deposition of photo resist. As modern photolithography seeks to define smaller and smaller feature size using shorter wavelength light, ultraviolet reflectivity becomes a greater problem, and thus the use of anti-reflection layer(s).
Eventually the wafer is passed by a robotic unit 140 to a bake plate 70 where the film of photoresist is hardened and excess solvents are driven out of the wafer with heat. A subsequent chill plate process 80 cools the wafers to a stabilized room temperature. Upon receipt of a track clock signal issued by computer system 40, the wafer under process is then sent out of the thus-described portion of track system 20 and is available for input to the stepper/scanner system 30. Stepper/scanner system 30 will accept the wafer in question responsive to a signal from the scanner clock. Within system 30 various lithographic techniques may be carried out upon the wafer in question. At module or step 90, the wafer is subjected to a post-exposure bake (PEB), using a PEB bake plate, and then to a chill plate 100, that returns the wafer to a stabilized ambient room temperature. A developer module stage 110 typically follows, during which the latent lithographic image that was formed within the stepper/scanner module 30 is developed in the polymer film on the wafer upper surface. In a positive tone image, the portions of the photoresist exposed to light will become soluble and dissolve away in solution to expose desired regions of the wafer structure. A bake plate step 120 follows to dry and harden the wafer surface. An etcher module 130 then follows, and the thus-processed wafer is returned to a chill plate, e.g., module 50. Several of the steps or stages shown in FIG. 1 may be repeated for the same wafer dozens of time, depending upon the specifics of the processes involved (e.g., the “recipe”. Typically devices shown generically as robotic arms 140 may be used to mechanically move wafers from one module to another.
In practice the rate at which track system 20 can send wafers for input to stepper/scanner system 30 may not coincide with the rate at which stepper/scanner system 30 is ready to receive (“R2R”) new wafers. Similarly, the time when scanner system 30 is ready to send (“R2S”) wafers back into track system 20 may not coincide with the moment at which track system 20 is ready to receive wafers for further processing. In some prior art systems 10, buffers such as 150 may be included to add time to processing of wafers within system 20. One or more buffers or buffer functions may be used in system 10 to absorb what would otherwise be disturbances to the time flow of wafers. A buffer may be a physical entity, for example a module used as a temporary storage site to hold excess wafers longer than needed for processing at that station, perhaps a dedicated buffer station, or a robotic arm temporarily used as a storage site for wafers.
By way of example, assume that responsive to timing of the track clock signal chill plate 80 is ready to send wafers into the stepper/scanner system 30 sooner than the stepper/scanner clock allows system 30 to be ready. When it is known that stepper/scanner system 30 is ready to receive wafers, the robotic arm 140 can load wafers into system 30, taking them if necessary from a buffer 150.
Understandably having to provide extra robotic arms and/or buffers to try to improve the output timing of track system 20 is not an optimum solution to the problem of enabling a better timing match between system 20 and system 30. There can be time conflicts within system 10 between modules competing for access to a given module, and it can be necessary to try to force time matching between wafers sent out of system 20, and wafers received into system 30, and then wafers exiting system 30 back into track system 20. But providing buffers 150 and/or additional robotic type mechanisms 140 to try to smooth out system flow requires additional cost and additional floor space within the fab, and will actually reduce wafer throughput.
One prior art solution to helping resolve resource conflicts within track system 20 is described in U.S. Pat. No. 6,418,356 (July 2002) to H. Oh, inventor herein. In the '356 patent, conflicts for transportation resources (e.g., robotic mechanism) are resolved by selectively adding “wait” time to modules that can tolerate such wait states without substantially degrading on-wafer production results associated with track system 20. Applicant incorporates herein by reference U.S. Pat. No. 6,418,356.
But even if track system resource conflicts can be resolved, deviations from nominal timing in the associated scanner system can degrade overall fabrication system performance. What is needed is a method of compensating for such scanner system timing deviations such that the timing match between the ready to send (R2S) state of the track system and the ready to receive (R2R) state of the stepper/scanner lithographic system is maintained.
The present invention provides such compensation for time deviations in a scanner system.